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9EX21501A idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?07/18/11 15 output pcie g2/qpi differential buffer with 2:1 input mux 1 datasheet functional block diagram description the ics9ex21501 provides 15 output clocks for pcie gen2 (100mhz) or qpi (133mhz) applications. a differential cpu clock from a ck410b+ main clock generator, such as the ics932s421, drives the ics9ex21501 . in fanout mode, the ics9ex21501 provides outputs up to 400mhz. a 2:1 input mux allows selection between local and remote clock sources. recommended application: 15 output pcie g2/qpi differential buffer with 2:1 input mux key specifications: ? dif output cycle-to-cycle jitter < 50ps ? dif output-to-output skew < 150 ps ? pcie gen2 compliant phase jitter ? qpi 6.4gb/s 12ui compliant phase jitter features/benefits: ? output clock frequencies up to 400 mhz/supports wide range of applications ? 4 selectable smbus addresses/multiple devices can share smbus segment ? smbus address independent of pll operating mode/ maximum flexibility ? dedicated ckpwrgd/pd# and vdda pins/easy board design ? 8 dedicated oe# and 2 group oe# pins/support for hardware clock management output features: ? 15 - 0.7v current-mode differential hcsl output pairs ? supports zero delay buffer mode and fanout mode ? selectable pll bandwidth ? 80-150 mhz in pll mode ? 33-400 mhz operation in bypass mode clka_in clka_in# dif(14:0) hibw_bypm_lobw# sel_a_b# smbdat smbclk ckpwrgd/pd# 15 iref oe13_14# oe(5:12)#, oe_01234# 10 smb_a0 smb_a1 100m_133m# clkb_in clkb_in# pll (ss compatible) logic
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 2 datasheet pin configuration vdd oe8# dif_8# dif_8 ckpwrgd/pd# sel_a_b# smb_a0 smb_a1 smbdat smbclk hibw_bypm_lobw# 100m_133m# dif_7# dif_7 oe7# vdd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 oe9# 1 48 dif_6# dif_9 2 47 dif_6 dif_9# 3 46 oe6# oe10# 4 45 dif_5# dif_10 5 44 dif_5 dif_10# 6 43 oe5# oe11# 7 42 dif_4# dif_11 8 41 dif_4 dif_11# 9 40 dif_3# gnd 10 39 dif_3 vdd 11 38 gnd dif_12 12 37 vdd dif_12# 13 36 dif_2# oe12# 14 35 dif_2 dif_13 15 34 dif_1# dif_13# 16 33 dif_1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd oe13_14# dif_14 dif_14# iref gnda vdda clka_in clka_in# gnd clkb_in clkb_in# vdd oe_01234# dif_0 dif_0# 9ex21501 64-pin mlf byte 0, bit 2 (100_133m# latch ) byte 0, bit 1 fsb byte 0, bit 0 fsa input mhz dif_x mhz notes 1 01 100.00 100.00 1 0 01 133.33 133.33 1 011 166.67 166.67 2 010 200.00 200.00 2 000 266.67 266.67 2 100 333.33 333.33 2 110 400.00 400.00 2 111 notes:100m_133m# 1. latch selects between 100 and 133 mhz. this is equivalent to fsc in ck410b+/ck509b fs table. 2. writing byte 2 bits (2:0) can select other frequencies. these frequencies are not characterized in pll mode frequency/functionality table reserved hibw_bypm_lobw# selection (pin 54) state voltage mode low <0.8v low bw mid 1.2 2.0v high bw smbus address selection (pins 57, 58) smb_a1 smb_a0 address 00d4 01d6 10d8 11da power groups power down functionality outputs ckpwrgd/pd# in p ut dif_x 1 runnin g runnin g on 0xhi-zoff pll state inputs vdd gnd 23 22 main pll, analog 29 26 input buffers 11,17,37,49, 64 10, 38 dif clocks description pin number
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 3 datasheet pin description pin # pin name type description 1oe9# in active low input for enabling dif pair 9. 1 = tri-state outputs, 0 = enable outputs 2 dif_9 out 0.7v differential true clock output dif_9# out 0.7v differential complement clock output 4 oe10# in active low input for enabling dif pair 10. 1 = tri-state outputs, 0 = enable outputs 5 dif_10 out 0.7v differential true clock output 6 dif_10# out 0.7v differential complement clock output 7 oe11# in active low input for enabling dif pair 11. 1 = tri-state outputs, 0 = enable outputs 8 dif_11 out 0.7v differential true clock output 9 dif_11# out 0.7v differential complement clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_12 out 0.7v differential true clock output 13 dif_12# out 0.7v differential complement clock output 14 oe12# in active low input for enabling dif pair 12. 1 = tri-state outputs, 0 = enable outputs 15 dif_13 out 0.7v differential true clock output 16 dif_13# out 0.7v differential complement clock output 17 vdd pwr power supply, nominal 3.3v 18 oe13_14# in active low input for enabling dif pairs 13 and 14 1 = tri-state outputs, 0 = enable outputs 19 dif_14 out 0.7v differential true clock output 20 dif_14# out 0.7v differential complement clock output 21 iref out this pin establishes the reference current for the differential current-mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 22 gnda pwr ground pin for the pll core. 23 vdda pwr 3.3v power for the pll core. 24 clka_in in true input for differential reference clock. 25 clka_in# in complement input for differential reference clock. 26 gnd pwr ground pin. 27 clkb_in in true input for differential reference clock. 28 clkb_in# in complement input for differential reference clock. 29 vdd pwr power supply, nominal 3.3v 30 oe_01234# in active low input for enabling dif pairs 0, 1, 2, 3 and 4. 1 = tri-state outputs, 0 = enable outputs 31 dif_0 out 0.7v differential true clock output 32 dif_0# out 0.7v differential complement clock output 33 dif_1 out 0.7v differential true clock output 34 dif_1# out 0.7v differential complement clock output 35 dif_2 out 0.7v differential true clock output 36 dif_2# out 0.7v differential complement clock output 37 vdd pwr power supply, nominal 3.3v 38 gnd pwr ground pin. 39 dif_3 out 0.7v differential true clock output 40 dif_3# out 0.7v differential complement clock output
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 4 datasheet pin description (continued) 41 dif_4 out 0.7v differential true clock output 42 dif_4# out 0.7v differential complement clock output 43 oe5# in active low input for enabling dif pair 5. 1 = tri-state outputs, 0 = enable outputs 44 dif_5 out 0.7v differential true clock output 45 dif_5# out 0.7v differential complement clock output 46 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 47 dif_6 out 0.7v differential true clock output 48 dif_6# out 0.7v differential complement clock output 49 vdd pwr power supply, nominal 3.3v 50 oe7# in active low input for enabling dif pair 7. 1 = tri-state outputs, 0 = enable outputs 51 dif_7 out 0.7v differential true clock output 52 dif_7# out 0.7v differential complement clock output 53 100m_133m# in input to select operating frequency. see frequency/functionality table for functionality of this pin. 54 hibw_bypm_lobw# in trilevel input to select high bw, bypass mode or low bw. 0 = low bw mode, mid= bypass mode, 1 = high bandwidth 55 smbclk in clock pin of smbus circuitry, 5v tolerant 56 smbdat i/o data pin of smbus circuitry, 5v tolerant 57 smb_a1 in smbus address bit 1 58 smb_a0 in smbus address bit 0 (lsb) 59 sel_a_b# in input to select differential input clock a or differential input clock b. 0 = input b selected, 1 = input a selected. 60 ckpwrgd/pd# in notifies the clock to sample latched inputs on the rising edge, and to power down on the fa lling edge. 61 dif_8 out 0.7v differential true clock output 62 dif_8# out 0.7v differential complement clock output 63 oe8# in active low input for enabling dif pair 8. 1 = tri-state outputs, 0 = enable outputs 64 vdd pwr power supply, nominal 3.3v
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 5 datasheet electrical characteristics - absolute maximum ratings parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v d d +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - clock input parameters ta = t com or t i nd; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (sin g le-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 400 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 750 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 2 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 50 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 50 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - phase jitter parameters ta = t com or t i nd; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 32/42 86 ps (p-p) 1,2,3,4 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2/1.5 3 ps (rms) 1,2,4 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.1/2.7 3.1 ps (rms) 1,2,4 t jphqpi qpi (133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.25/0.28 0.5 ps (rms) 1,4,5 t jphpcieg1 pcie gen 1 2 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.0 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.30 0.5 ps (rms) 1,2,6 t jphqpi qpi (133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.25 0.4 ps (rms) 1,5,6 1 applies to all outputs. device driven by idt ck410b+ (932s421cglf) or equivalent 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total ji ttter)^2 - (input jitter)^2 4 first number is low bw , second number is hi bw. 5 calculated from intel-su pp lied clock jitter tool v 1.6.4 , with 7.8m rolloff phase jitter, pll mode additive phase jitter, bypass mode t jphpcieg2 t jphpcieg2 2 see htt p ://www. p cisi g .com for com p lete s p ecs 3 sam p le size of at least 100k c y cles. this fi g ures extra p olates to 108 p s p k- p k @ 1m c y cles for a ber of 1-12.
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 6 datasheet electrical characteristics - input/supply/common parameters ta = t com or t ind; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes t com commmercial range 0 25 70 c 1 t ind industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2 2.400 v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.400 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull- down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 33 400 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 80 100.00 110 mhz 2 f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 150 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.5 1 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 10 12 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 0.2 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.4 0.8 v 1 smbus input high voltage v ihsmb 2.1 2.4 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.3 0.4 v 1 smbus sink current i pullup @ v ol 45 ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 3.3 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 100 khz 1,5 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swin g . 4 dif_in input 5 the differential in p ut clock must be runnin g for the smbus to be active. tested at fin=100mhz. 3 time from deassertion until out p uts are >200 mv input current input frequency capacitance ambient operating temperature
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 7 datasheet electrical characteristics - dif 0.7v current mode differential outputs ta = t com or t i nd; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1 2.2 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 11 20 % 1, 2, 4 voltage high vhigh 660 772 850 1 voltage low vlow -150 10 150 1 max voltage vmax 870 1150 1 min voltage vmin -300 -47 1 vswing vswing scope averaging off 300 1390 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 360 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 14 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any system. note that this is a subset of v_cross_min/max (v_cross absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than v_cross absolute. 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? (100 ? differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate of clock / fa lling edge rate of clock#. it is measured in a +/-75mv wi ndow centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). statistical measurement on single- ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging mv electrical characteristics - current consumption ta = t com or t ind; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes i dd3.3vddop ta - t com , all outputs active <200mhz 306 330 ma 1 i dd3.3vddop ta - t com , all outputs active >=200mhz 360 390 ma 1 i dd3.3vddaop ta - t com , all outputs active <200mhz 29 36 ma 1 i dd3.3vddaop ta - t com , all outputs active >=200mhz 29 36 ma 1 vdd powerdown current, commerical temp i dd3.3vddpdz ta = t com , all differential pairs hi-z 12 15 ma 1 vdda powerdown current, commercial temp i dd3.3vddapdz ta = t com , all differential pairs hi-z 15 20 ma 1 i dd3.3vddop ta - t ind , all outputs active <200mhz 325 350 ma 1 i dd3.3vddaop ta - t ind , all outputs active >=200mhz 390 420 ma 1 i dd3.3vddop ta - t ind , all outputs active >=200mhz 33 40 ma 1 i dd3.3vddaop ta - t ind , all outputs active >=200mhz 33 40 ma 1 vdd powerdown current, industrial tem p i dd3.3vddpdz ta = t ind , all differential pairs hi-z 15 20 ma 1 vdda powerdown current, industrial temp i dd3.3vddapdz ta = t ind , all differential pairs hi-z 16 20 ma 1 1 guaranteed by design and characterization, not 100% tested in production. vdd operating current, commerical temp vdda operating current, commercial temp vdd operating current, industrial temp vdda operating current, industrial temp
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 8 datasheet electrical characteristics - skew and differential jitter parameters ta = t com or t ind; supply voltage vdd/vdda = 3.3 v +/-5%, see test loads for loading conditions parameter symbol conditions min typ max units notes clk_in, dif[x:0], 100m t spo_pll100m input-to-output skew in pll mode nominal value @ 25c, 3.3v 925 1019 1125 ps 1,2,4,5,8 clk_in, dif[x:0], 133m t spo_pll133m input-to-output skew in pll mode nominal value @ 25c, 3.3v 1100 1120 1200 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 4 4.6 5.2 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across voltage and temperature |258| |350| ps 1,2,3,5,6 ,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across voltage and temperature |771| |900| ps 1,2,3,5,6 ,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9ex2 devices in hi bw mode 210 ps (rms) 1,2,3,5,8 ,12 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9ex2 devices in hi bw mode 20 75 ps 1,2,3,5,8 ,13 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 75 150 ps 1,2,8 pll jitter peaking j p eak-hibw high bandwidth 0 2.3 3 db 7,8 pll jitter peaking j p eak-lobw low bandwidth 0 2.5 3 db 7,8 pll bandwidth pll hibw high bandwidth 2 2.5 4 mhz 8,9 pll bandwidth pll lobw low bandwidth 0.7 0.87 1.4 mhz 8,9 duty cycle t dc measured differentially, pll mode 45 49.6 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 0.2 2 % 1,10 pll mode 27 50 ps 1 additive jitter in bypass mode 20 50 ps 1 notes for preceding table: 7 measured as maximum pass band g ain. at frequencies within the loop bw, hi g hest point of ma g nification is called pll jitter peakin g . 8. guaranteed by desi g n and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mo d 11 measured from differential waveform 13 differential spread spectrum tracking error is the difference in spread spectrum tracking between two ics9ex21501 devices th is parameter is measured at the outputs of two separate ics9ex21501 devices driven by a single ck410b+ in spread spectrum mode. the ics9ex21501's must be set to high bandwidth. the spread spectrum characteristics are: maximum of 0.5%, 30-33khz modulation frequency, triangle profile. 6. lon g -term variation from nominal of in p ut-to-out p ut skew over tem p erature and volta g e for a sin g le device. 12. this parameter is measured at the outputs of two separate ics9ex21501 devices driven by a single ck410b+. the ics9ex21501's must be set to high bandwidth. differential phase jitter is the accumulation of the phase jitter not shared by th e outputs (eg. not including the affects of spread spectrum). target ranges of consideration are agents with bw of 1-22mhz and 11-33mhz. jitter, cycle to cycle t jcyc-cyc 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross-point to differential cross-point. 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this p arameter is deterministic for a g iven device 5 measured with sco p e avera g in g on to find mean value.
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 9 datasheet rs hcsl output rs rp rp hcsl differential output test load 2pf 2pf zo= differential impedance differential output termination table dif zo ( ? )iref ( ? )rs ( ? )rp ( ? )c l (pf) 100 475 33 50 2 test load 85 412 27 43.2 2
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 10 datasheet general smbus serial interface information for the 9ex21501 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends the beginning byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d5 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d4 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d5 (h) index block read operation slave address d4 (h) beginning byte = n ack ack note: smbus address is selectable among 4 addresses. see tabel on page 2.
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 11 datasheet 9ex21501 smbus addressing ` smb adr: dc 9db403/803 (db400e/800e) smb adr: d2 (ck410b+/ck509b) smb_a(1:0) = 10 smb adr: d8 smb_a(1:0) = 11 smb adr: da smb_a(1:0) = 00 smb adr: d4 smb_a(1:0) = 01 smb adr: d6 smb_a(2:0) = 100 smb adr: d8 smb_a(2:0) = 101 smb adr: da smb_a(2:0) = 110 smb adr: dc smb_a(2:0) = 111 smb adr: de smb_a(2:0) = 000 smb adr: d0 smb_a(2:0) = 001 smb adr: d2 smb_a(2:0) = 010 smb adr: d4 smb_a(2:0) = 011 smb adr: d6 or or or or or or 9ex21501 (db1200g/gs) (db1900g/gs) (db1200g/gs) (db1900g/gs) (db1200g/gs) (db1900g/gs) 9ex21501 (db1200g/gs) (db1900g/gs) (db1200g/gs) (db1900g/gs) (db1200g/gs) (db1900g/gs) (db1200g/gs) (db1900g/gs) (db1200g/gs) (db1900g/gs) 9ex21501 9ex21501
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 12 datasheet smbustable: output, and pll bw control register pin # name control function t yp e0 1default bit 7 rw latch bit 6 rw latch bit 5 1 bit 4 dif_14 output control rw hi-z enable 1 bit 3 0 bit 2 100m_133m# frequency select bit c rw 133mhz 100mhz latch bit 1 fsb frequenc y select bit b r w 0 bit 0 fsa frequency select bit a rw 1 smbustable: output control register pin # name control function t yp e0 1default bit 7 1 bit 6 dif_6 output control r w hi-z enable 1 bit 5 dif_5 output control rw hi-z enable 1 bit 4 dif_4 output control rw hi-z enable 1 bit 3 dif_3 output control rw hi-z enable 1 bit 2 dif_2 output control r w hi-z enable 1 bit 1 dif_1 output control rw hi-z enable 1 bit 0 dif_0 output control rw hi-z enable 1 smbustable: output control register pin # name control function type 0 1 default bit 7 dif_13 output control rw hi-z enable 1 bit 6 1 bit 5 dif_12 output control rw hi-z enable 1 bit 4 dif_11 output control r w hi-z enable 1 bit 3 dif_10 output control rw hi-z enable 1 bit 2 dif_9 output control rw hi-z enable 1 bit 1 dif_8 output control rw hi-z enable 1 bit 0 dif_7 output control rw hi-z enable 1 smbustable: output enable readback register pin # name control function t yp e0 1default bit 7 oe10# input pin readback r pin low pin hi x bit 6 oe9# input pin readback r pin low pin hi x bit 5 oe8# input pin readback r pin low pin hi x bit 4 oe7# input pin readback r pin low pin hi x bit 3 1 bit 2 oe6# input pin readback r pin low pin hi x bit 1 oe5# input pin readback r pin low pin hi x bit 0 oe_01234# input pin readback r pin low pin hi x reserved reserved reserved reserved 00 = low bw (1mhz) 10 = bypass 11 = high bw (3mhz) see frequency select table b y te 3 63 30 46 43 50 1 4 pll_bw# adjust bypass# test m ode / pll - 54 - - b y te 1 b y te 2 b y te 0 reserved
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 13 datasheet smbustable: output enable readback register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 100m_133m# input pin readback r 133m 100m x bit 4 sel_a_b# input pin readback r input b input a x bit 3 oe13_14# input pin readback r pin low pin hi x bit 2 1 bit 1 oe12# input pin readback r pin low pin hi x bit 0 oe11# input pin readback r pin low pin hi x note: for an output to be enabled, both the output enable bit and the oe# pin must be enabled. this means that the output enable bit must be '1' and the corresponding oe# pin must be '0'. smbustable: vendor & revision id register pin # name control function t yp e0 1default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e0 1default bit 7 r0 bit 6 r0 bit 5 r0 bit 4 r1 bit 3 r1 bit 2 r0 bit 1 r0 bit 0 r0 smbustable: byte count register pin # name control function t yp e0 1default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 r w --0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 r w --1 bit 0 bc0 rw - - 1 reserved reserved reserved device id 2 device id 3 device id 4 b y te 6 b y te 7 - - - - - - 14 b y te 5 - - b y te 4 device id 1 writing to this register configures how many bytes will be read back. - - - - - - 7 - - - - 18 - device id 6 device id 7 (msb) vendor id - - - - - revision id device id 0 device id 5 device id is 18 hex
idt ? 15 output pcie g2/qpi differential buffer with 2:1 input mux 1578?01/18/11 9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 14 datasheet dimensions dimensions (mm) symbol min. max. a0.81.0 n64 a1 00.05 n d 16 a3 n e 16 b 0.18 0.3 e d x e basic d2 min. / max. 7.00 7.25 e2 min. / max. 7.00 7.25 l min. / max. 0.30 0.50 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package 0.25 reference 0.50 basic 9.00 x 9.00 ordering information part / order number shipping packaging package temperature 9EX21501Aklf trays 64-pin mlf 0 to +70 c 9EX21501Aklft tape and reel 64-pin mlf 0 to +70 c 9EX21501Akilf trays 64-pin mlf -40 to +85c 9EX21501Akilft tape and reel 64-pin mlf -40 to +85c "lf? suffix to the part number are the pb-free configuration and are rohs compliant. "a" is the revision designator (will not correlate with datasheet revision). due to package size constraints actual top side marking may differ from the full orderable part number.
9ex21501 15 output pcie g2/qpi differential buffer with 2:1 input mux 15 datasheet innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2011 integrated dev ice technology, inc. all right s reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa revision history rev. who issue date description page # 0.1 rdw 4/6/2009 initial release - 0.2 rdw 4/7/2008 1. lowered idd 2. updated block diagram to correct typo's 3. corrected pin descriptions 4. corrected frequency/functionality table references to byte 2, should be byte 0 5. updated power groups table 6. corrected typo in smbus address selection table. 7. corrected references to 9ex1501 to be 9ex21501 various 0.3 rdw 11/24/2009 1. added more detailed idd numbers to ds 2. added industrial temp idd numbers and ordering information 0.4 rdw 2/4/2010 1.corrected pin description for pin 52. there was descrepancy between the frequency/functionality table and the pin description. the pin description was not correct. instead of the pin description defining functionality, it now refers to the frequency functionality table for the definition. 4 0.5 rdw 1/18/2011 1. reformatted electrical tables to latest template 2. updated electrical tables with characterized data 3. added test loads diagram and table 4. move to final various

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